A unified architecture of MD5 and RIPEMD-160 hash algorithms

Hash algorithms are important components in many cryptographic applications and security protocol suites. In this paper, a unified architecture for MD5 and RIPEMD-160 hash algorithms is developed. These two algorithms are different in speed and security level. Therefore, a unified hardware design allows applications to switch from one algorithm to another based on different requirements. The architecture has been implemented using Altera's EPF10K50SBC356-1, providing a throughput over 200Mbits/s for MD5 and 80Mbits/s for RIPEMD-160 when operated at 26.66MHz with a resource utilization of 1964LC.published_or_final_versio

Buffer control algorithm for low bit-rate video compression

In this paper, a new buffer control algorithm for motion-compensated hybrid DPCM/DCT coding (like H.261 and MPEG-1 I pictures) is presented. The algorithm uses the bit allocation algorithm to determine the quantization scale factor of each macroblock under a given target bit rate. An important advantage of the algorithm is that it has precise control of the buffer and avoids buffer overflow events which is a severe problem in low bit rate video coder. Furthermore, the coder is able to allocate bits to the picture as a whole, resulting in better rate-distortion trade-off. Simulation results show that the H.261 coder, using the proposed algorithm, can achieve a higher PSNR and better visual quality than codec using conventional buffer control algorithm.published_or_final_versio

Tri-Level Bit-Stream Signal Processing Circuits and Applications

We present signal processing building blocks for trilevel bit-stream signal processing (BSSP). These architectures are the 2-bit extensions from the existing 1-bit BSSP circuit modules. It is shown that the 2-bit designs offer better performance than their 1-bit counterparts. FPGA implementation results of both 1-bit and 2-bit designs are compared in terms of their hardware complexity. Finally, a digital phase locked loop (DPLL) and a quadrature phase-shift keying (QPSK) demodulator are presented as application examples of the proposed circuits.published_or_final_versio

Bit-stream adders and multipliers for tri-level sigma-delta modulators

We propose both adder and multiplier circuits for bit-stream signal processing customized for tri-level sigma-delta modulated signals. These architectures are the 2-bit extensions from the existing 1-bit bit-stream adders and multipliers, and are shown to offer better signal-to-noise performance. Field-programmable gate array implementations then confirm their efficacy. © 2007 IEEE.published_or_final_versio

An adaptive multiresolution modification of the H.263 video coding algorithm

An adaptive multiresolution approach for video coding is presented. The algorithm uses the information content to determine the resolution of the video to be encoded. An important advantage of the algorithm is that the codec can maintain a very stable frame rate with reasonable image quality during scene change and provide better quality video when the motion is less rapid. Simulation results show that the modified H.263 coder, using the proposed algorithm, can maintaining better image quality and a more steady frame rate than the TMN 5 algorithm at low bit-rate.published_or_final_versio

A multiresolution two-layer video codec for networking applications

We propose an improved multiresolution two-layer video codec that can operate at a base layer of 64 kbps and a variable bit rate second layer (VBR). The basic idea is to use a multiresolution technique to reduce the original CIF format video to the QCIF format. The low-resolution video is then encoded with an improved H.261 codec. To reduce the bit rate of the second layer, the residuals are encoded with the discrete cosine transform (DCT) using perceptually weighted quantization step sizes. Simulation results show that the Miss America sequence can be transmitted at 64 kbps in the CIF format with a reasonably good picture quality. For a good picture quality, the second layer would typically require 190 kbps.published_or_final_versio

A modified H.263 algorithm using bit allocation buffer control algorithm

Buffer control is an important problem in very low bitrate video coding. In a recent work [ 111, the authors had proposed a new buffer control algorithm for motion-compensated hybrid DPCMiDCT coding. The algorithm is based on the use of bit allocation algorithm to determine the quantization scale factors in such coder to meet a given target bit rate. Simulation results showed that, using the proposed algorithm, the H.261 coder can achieve a higher PSNR and better visual quality than the coder using traditional buffer control algorithm. In this paper, we apply this buffer control algorithm to a modified version of the H.263 algorithm for very low bit-rate video coding. Comparing the performance of the modified H.263 codec with the TMN5 model also shows that better visual quality can be obtained at comparable PSNR values.published_or_final_versio

Partial-encryption technique for intellectual property protection of FPGA-based products

The configuration-data sequence of a field-programmable gate array (FPGA) is an intellectual property (IP) of the original designer. This paper proposes a partial-encryption (PE) technique for IP protection of configuration-data sequences by means of increasing the reverse-engineering cost. The PE technique encrypts a few selected data of the sequence. These data are selected in a judicious way such that, when a rival competitor copies the partially encrypted sequence into a cloned product, the cloned product performs the expected task to a certain degree of correctness but not absolutely error-free. Debugging is required. It is shown that, without an initial knowledge that a reverse-engineering countermeasure is employed, the PE technique outperforms the full-encryption technique in terms of the reverse-engineering cost. This paper describes implementation details of the proposed PE technique. Issues regarding system designs that embed hidden imperfections are also discussed.published_or_final_versio

A CDMA Receiver Using Exponentially Weighted Despreading Waveforms

This paper presents a DS-CDMA receiver using exponentially weighted despreading waveforms (WDW). The chip weighting waveforms are designed for the purpose of multiple access interference (MAI) rejection by emphasizing the transitions of the received signal of interest. The WDW is determined only by one parameter, which leads to easy tuning of the WDW in practice to achieve the best performance. As a result, we show that the proposed receiver can reject MAI without knowing co-user's spreading codes, timing, and phase, and hence increase system capacity. Analysis and numerical results show that the proposed receiver outperforms the conventional receiver especially when MAI is significant. Finally, a discussion on the effect of bandlimited spreading signals is also given on the practical implications of the proposed technique.published_or_final_versio

Timing estimation for quasi-synchronous SDMA systems

In this paper, timing estimation for quasi-synchronous SDMA systems is considered. The problem arises in the uplink of a mobile communication system where precise synchronization among all mobiles is very difficult to be achieved and signals of all mobiles are time-aligned at the receiver within a small synchronization window. An efficient timing estimation method is proposed. It can simultaneously estimate the channel responses and the time delays which are required for signal detection. Simulation results show that the time delays can be accurately estimated and the performance of MMSE multi-user detection with the proposed method is very close to that with the perfect timing and channel information.published_or_final_versio